A LOOK INSIDE THE CARTESI ARCHITECTURE

Cartesi is a blockchain-based solution to develop and develop decentralized applications. Cartesi is a platform designed as a solution to the scalability, interoperability, and the decentralization issues that even the latest blockchain platforms face. As a solution, it has combined off-chain and blockchain. This makes it highly scalable, with the ability to provide high throughput. The off-chain element of the Cartesi, work due to the Cartesi Nodes. Cartesi Nodes give the users the intricate Cartesi Machines. It executes and processes massive verifiable computations by using Cartesi Machines. Cartesi Machine is designed with Linux operating system, with great features like strong conflict-resolution protocol.

The Cartesi Machines
Cartesi Machine is computational that is an autonomous and established model. It is designed to host the latest operating system. The interactive computations involving the real-world problems and solutions occur within an operating system. The developers are prepared for using toolchains and function at the greatest level of generalization for any kind of project, separating the tools from the specifics of the particular operating system. So, whenever a novel architecture is devised impromptu, the toolchain and operating system would entail porting. Therefore, while designing Cartesi Machines, they were based on an established architecture. The toolchain and operating system for it are even now available and familiar to a standard developer.

Cartesi Machines can only perform an off-chain computation that is verifiable by a blockchain. To be able to execute this, blockchain the whole architecture must have a reference implementation hosted by the blockchain. This implementation needs to be auditable, open and reasonably simple. This way it would remain reliable and trusted. These conditions indicate that RISC-V would be a suitable architecture. RISC-V ISA is designed on the foundation of the minimal 32-bit integer instruction set. Numerous extensions can be included in 32-bit. Operand and address-space width can be increased to 64-bits. The specifications characterize a privileged architecture. The features involved are timers, exceptions, multifold privilege levels, traps, and page-based virtual memory.

RISC-V was invented in UC Berkeley. It is maintained independently by its institution. Corporate giants like Google, Tesla, and Samsung are also taking part in the whole project. The best team of developers has come up with comprehensive software infrastructure. It includes the Linux OS ports and the efficient GNU toolchain. The architecture of RISC-V is designed for direct native implementation of hardware. With continuous developments, it can be foreseen that Cartesi will not remain restricted to emulation and binary translations occurring off-chain.

Cartesi Machines have two distinct components-processor and aboard. The processor executes computations and performs the conventional fetch-execute loop, at the same time maintaining a range of registers. The ecosystem is defined with a variety of memories and devices by the board. Cartesi Machines have a well-defined method to allow verifications to take place. The entire state, including the board, internal states of the processor, and all the connected devices, is mapped in physical memory in a precise mechanism. This modification within the architecture does not restrict the OS or the hosted application in any way.